1. Field of the Invention
The present invention relates to a copper line of a semiconductor device and a method for forming the same, and more particularly, to a copper line of a semiconductor device and a method for fabricating the same with a damascene process.
2. Discussion of the Related Art
Generally, a metal line of a semiconductor device is formed of a metal thin film such as aluminum, aluminum alloy or copper. The metal line is connected to a circuit formed on a semiconductor substrate through an electric connection and a pad contact.
According to the related art, a contact hole is formed by selectively etching through on insulating layer, and then a metal plug is formed by depositing barrier metal and tungsten in the contact hole. After that, a metal thin film is deposited and patterned on the metal plug, thereby forming the metal line used to contact the device electrode with the pad.
Generally, the metal line is patterned by photolithography. According to the trend for miniaturization of semiconductor devices, the critical dimension (CD) of the metal line decreases as the device size decreases. It is difficult to obtain small patterns for metal lines. To overcome this problem, it has been proposed to form small metal line patterns using a damascene process.
In a damascene process, a tungsten plug is formed in a contact hole then an upper insulating layer of oxide is formed over the insulating layer and the plug. The upper insulating layer is then patterned by photolithography to form the metal line patterns. A metal thin film is then formed inside the metal line patterns, and is subsequently planarized by CMP (Chemical Mechanical Polishing), to form a metal line layer.
FIGS. 1 to 3 are cross sectional views of illustrating some steps for fabricating a semiconductor device according to the related art.
As shown in FIG. 1, a lower metal layer 110 is formed on a semiconductor substrate 100, then an IMD (Inter Metal Dielectric) 125 is formed over the entire surface of the semiconductor substrate 100 and over lower metal layer 110. A copper layer is formed on the exposed lower metal layer 110 and the IMD 125, and is then planarized by CMP, thereby forming a copper line 145. However, according to this process, dishing 108 may be generated in the surface of the IMD 125 when performing the CMP step.
As shown in FIG. 2, an upper IMD 150 is formed on the IMD 125. However, when doing so, dishing 118 may be also generated in the surface of the upper IMD 150, wherein the dishing 118 formed in the surface of the upper IMD 150 is same in shape as the dishing 108 formed in the surface of the IMD 125.
Referring to FIG. 3, the copper line 145 is exposed by patterning the upper IMD 150, and then forming an upper copper layer on the exposed copper line 145 and the upper IMD 150. Upper copper line 175 is completed by another CMP step that planarizes the upper copper layer. When doing so, the copper residue 198 that is generated is collected on the surface of the upper IMD 150 due to the dishing 188. The presence of this copper residue on the surface of the upper IMD 150 is problematic because it causes the disconnection of the upper copper lines 175.
To prevent the disconnection of the copper line, the prior art uses a dummy area method. However, the dummy area method has the problem of increasing capacitive coupling and noise in a dummy area when being applied to a mixed signal technology.